
Hardware IP Verification Methodology Lead
- Cambridge
- Permanent
- Full-time
- Define a top-down Design Verification Strategy for the next generation IP.
- Work with all Subsystem leaders to define a DV strategy that fits into the overall strategy.
- Lead the development and deployment of cutting-edge verification tools and methodologies.
- Assess existing testbench infrastructure and work with the teams to agree priorities for development/improvements.
- Work with the project management team to align on DV schedule and resources.
- Track DV metrics across the project and help to make real-time corrections to DV planning and execution. Escalate risk and opportunities to engineering and project Management.
- Take part in DV Strategy, Planning and Signoff reviews and act as an ultimate gate for DV signoff.
- Foster a culture of innovation, top quality, and technical excellence
- Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field
- Minimum 15 years of relevant industry experience in SOC and IP Design Verification.
- Demonstrate deep expertise in Verification tools and Methodologies (e.g. UVM, Formal Verification, FPGA/Emulation, System level verification) as well as in RTL design (Verilog, SystemVerilog) and scripting languages (Python, Shellscript)
- Proven track record of successful tape-outs on time of major IP and SOCs.
- Experience leading large multi-national teams on complex semiconductor projects.
- Solid experience verifying memory interfaces (LPDDR, HBM, GDDR), communication protocols (Mipi, HDMI, SPI, USB, etc)
- Knowledge/Interest in AI applications to Si DV flow
- GPU IP experience a definitive plus
- Excellent communication, leadership, and problem-solving skills, with the ability to work effectively within global, cross-functional teams