
CPU Design Verification Engineer (Sr. Staff)
- Cambridge
- Permanent
- Full-time
- Perform functional feature verification of high-speed Microprocessor designs, including the development of infrastructure, directed and random test suites at behavioral RTL level across SoC, Core, and block hierarchies.
- Develop environments, infrastructure, and test plans to accommodate both full chip and stand-alone block-level verification and debug capabilities using simulation tools, debug tools, and programming skills, based on an in-depth understanding of the microprocessor's architecture and HDL/logical design.
- Develop an automated regression infrastructure setup for functional verification of high-speed microprocessor designs.
- Based on a thorough understanding of the design architecture, develop, run, and debug x86 assembly-based directed tests and random exercisers to validate functionality and testability operation of the microprocessor design, leveraging C/C++/Perl/assembly programming, logic design, and simulation skill set.
- Resolve all simulation discrepancies and assertion responses for both behavioral and gate-level logic models.
- Measure and analyze coverage results and take necessary actions to fill in coverage holes.
- Understanding or technical expertise in functional verification of microprocessor designs.
- Experience with Verilog/System Verilog HDL, programming in Perl, C/C++, and logic simulation is a requirement.
- Direct experience with Verilog simulators is a plus.
- Very strong understanding of computer architecture and assembly programming.
- Good communication skills.
- MS or Ph.D. with some industry co-op experience desired (all degrees are related to CS or EE).
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