Contribute to IP library in SystemVerilog and build out complete FPGA design solutions for customers.Deliver highly performant, well tested and extensible code for some of the most widely deployed AI in modern data centers.Responsibilities:Writing and testing IP components in SystemVerilog for FPGABuilding full applications for FPGA using our IP libraryIntegrating with third party IP for external memory PCIe subsystemsExtending IP verification code and integrating into automated test environmentsWorking with software interface routines to support FPGA integration into the software stacksLearning about a range of Machine Learning inference optimization techniquesProviding technical support for customer engagementsRequirements:Masters degree in Engineering, Mathematics or other Scientific DisciplineAt least 5 years' experience generating clear, well-documented, and well-tested SystemVerilog, Verilog or VHDL codeExperience simulating and verifying large RTL designsWorked with FPGA EDA tools such as Quartus or VivadoWorked with software languages such as C, C++, PythonFamiliarity with Linux development environments, version control and C I systems
